Recently, attention is given to a Ge-FinFET having an FET formed with a Ge-fin structure formed on the bulk Si. The Ge-FinFET has some issues, such as deterioration in mobility due to non-uniformity of the channel plane orientation, variation in threshold voltage due to line-edge-roughness (LER) and variation in leakage current. In the prior art that the Ge layer is epitaxially grown on the region where the Si substrate is recessed after forming the STI on the Si substrate, it is not realized to make a (110) plane with high mobility on the channel side surface because the channel plane orientation becomes non-uniform due to the tapered shape caused by the STI (C-T Chung et. al., Ext. Abst. of 2009 Int. Conf. on SSDM (2009) pp 174-175).
Further, in the region in which the fin width is not larger than 50 nm and the fin pitch is not larger than 150 nm, it is difficult to apply a stress to the channel by using such as a contact etching stop liner (CESL) film due to the limited space in the S/D region. Further, it is difficult to efficiently apply a strain to the Ge-fin structure since a stressor itself is processed by fin etching if the stressor is inserted into the underlying layer.